gtdigital®

Schematic Capture with Cadence OrCad and
Simulation with PSPICE, Mentor HyperLynx, and XILINX Tools

J. Bellott, MSEE

(Rev 3.0))

Contents

Introduction

OrCad Features

OrCad Schematic Example

PSPICE Simulation Features

DC ANALYSIS

AC ANALYSIS, Non-Sinusoidal Inputs (Time domain)

AC ANALYSIS, Sinusoidal Inputs (Time domain)

FREQUENCY ANALYSIS (Using phasors and real impedances)

FOURIER ANALYSIS (Frequency Domain)

Mentor HyperLynx Pre- and Post-Layout Simulation of Schematics

XILINX BERR Simulation of Differential Pairs

Design Verification in the Lab

Useful Links

 

Figure

Figure 1 - MCU Schematic Page

 

 

Introduction

 

This technical note provides and overview of Cadence OrCad features for drawing schematics, simulating using SPICE, and Mentor HyperLynx Line Sim and Board Sim tools for pre- and post-layout simulation of critical nets and buses.

 

OrCad Features

 

OrCad saves a set of drawings as a “project.”

Project types include:

·         Digital schematics

·         Schematics with analog and digital parts

·         Programmable Logic

 

Project libraries are maintained by OrCad which contain a copy of cached part models from the parts database or library.

 

OrCad CIS can use the internet to access a large on-line library of part libraries. The part libraries include OrCad symbols, Layout symbols, and simulation models.

 

Each OrCad Schematic Capture part has a list of attributes that can be edited, including the part reference designators, values, package types, and manufacturer.

 

OrCad can generate a BOM and also provides input to OrCad layout tools.

 

OrCad Schematic Example

 

OrCad allows one to place parts on schematic pages using a database library. The library can be extended by drawing your own parts and adding them to the database or buy purchasing on-line access to the OrCad CIS database of parts for a wide variety of applications.

 

The drawing below is an 80251 schematic. (The page shown is not complete; some additional connections are required for chip enables, port mode selection, and external timers and interrupt pins.) A 2007 survey of the world’s top microcontrollers placed the x51 family as #1, with a trend to reduction in market share. Other popular MCU’s included ARM core based products (made by TI, Freescale, NPX (Phillips), and others. Also MicroChip PIC and dsPIC MCU’s, and TI microcontrollers. See www.gtdigitalsite.org/home/techlinks and view the “Microcontrollers” section for a list of the top ten MCU’s by sales. ARM was the first company to produce a licensable, reusable standards based core model description for use on SOC’s in the 1990’s.

The modern instruction set compatible x51 family is now produced by multiple vendors, and includes address space extensions and a full complement of modern peripherals. (e.g. I2C, SPI, others). See the Mirochip 8051 part on www.microchip.com as an example of an updated x51 architecture part.

 

The original Intel 80251 has 4 optional ports. Using internal ROM, all four ports can be enabled for external access to other parts in the application. The 80251 can also address external ROM, RAM, and I/O parts can also be addressed. Chip enables allow the designer to access individual external parts conveniently.

 

Timer outputs T0-T2 permit the user to output strobe signals with pre-programmed timing. The 80251 also has programmable interrupts when the timers expire. Timers can be programmed to re-initialize and continue. Interrupts can occur repetitively or upon a single timer count down.

 

A synchronous WAIT input halts the processors transactions.

 

The 80251 also has two Interrupt inputs that permit the microcontroller to serve external functions on demand.

 

Using the extended addressing capability of this 80251 microcontroller, A0-A17 are available. This permits addressing of up to 256KB of address space.

 

 

Figure 1 - MCU Schematic Page

 

The OrCad window on the left provides a list of files and folders saved with the OrCad project. The schematic project has the suffice .DSN. The schematic folder contains each page of the project schematics (in this case, PAGE1). The Design Cache contains a list of library database parts accessed and loaded as part of the project.

 

The PART MANAGER window at the top of the screen shows a list of all parts used in the design. It includes their reference names, values, Part Numbers, location of the source library, package types, and other information.

 

 

PSPICE Simulation Features

 

OrCad was originally created as a tool for drawing circuits and simulating them using SPICE in a graphical environment. The program was purchased by CADENCE and has been extended to include all of its modern schematic capture features as a complete tool for PCB and programmable device design projects.

These types of simulation are available using SPICE in OrCad:

DC ANALYSIS

1. Voltage source is specified; one can compute node voltages, currents, power dissipation.

2. Step and repeat DC analysis for different voltage source values.

 

AC ANALYSIS, Non-Sinusoidal Inputs (Time domain)

Circuit response to user specified Input Waveform from a voltage source including

a. Exponential rise and fall,

b. Pulse train with specified linear slew rates on leading and trailing edges, and

c. Switches (response of circuit to switches being opened or closed).

 

AC ANALYSIS, Sinusoidal Inputs (Time domain)

Basic models include not only passives, voltage and current sources, but also ICVS (as in NPN and PNP transistors), ICIS, VCVS, and VCIS

1. Circuit analysis in response to Sinusoidal Inputs of a fixed frequency; transient response (at first) and steady state response (observed later).

2. Swept Sinusoidal Input voltages and circuit responses for each frequency (step frequency and repeat).

 

FREQUENCY ANALYSIS (Using phasors and real impedances)

1.       Frequency Analysis using phasors and real impedances, fixed frequency, steady state.

Voltages (and currents) in circuit are represented as phasors comprising magnitude and phase (real and imaginary components).

In essence, a phase is relative to other phases in the circuit.

Impedance (Z) of elements have real and imaginary components.

BENEFIT: One can use SPICE to understand the voltage (or current) magnitude and phase of any node (or path).

2.       Frequency Analysis using phasors and real impedances, frequency values are stepped and repeated.

Example use: Audio circuits are sometimes designed to have approximately linear phase response in the frequencies of interest.

Phase shifts outside of the circuit goals are less important and might be non-linear or less linear.

 

FOURIER ANALYSIS (Frequency Domain)

Periodic input signal, steady state operation.

For any node voltage (or current path), a Fourier expansion of the simulation signal is used to determine the Fourier coefficients and component frequencies.

BENEFIT: DETERMINE MAGNITUDE AND FREQUENCY OF SPECTRAL COMPONENTS OF SIGNALS

Other useful values that are useful in some applications can be derived: SNR, THD.

 

SPICE provides both tabular results information and graphical plots. A CAPSYM off page reference is used to name nets that represent circuit output values of interest. The net label names appear in the SPICE results.

 

The user can specify what type of information should be plotted. Time, frequency, signal value (voltage or current magnitude using linear or log values, phase angles, etc) are among the types of output values.

 

Mentor HyperLynx Pre- and Post-Layout Simulation of Schematics

 

In some cases, schematic pages contain high speed signals or differential pairs that must be modeled as transmission lines.

 

Before layout, Mentor HyperLynx Line Sim can be used to stimulate and measure the characteristics of high speed signals, including reflections, crosstalk, ringing, and other characteristics.

 

Mentor HyperLynx Board Sim is a post layout tool which takes into account the actual routing net list and board geometry prepared by Mentor layout tools for PADS schematics or OrCad family layout tools (Allegro).

 

HyperLynx uses models available directly from manufacturers (IBIS) or user constructed table based models, among the numerous model types supported.

 

HyperLynx wizards are available to quickly map net list sections to key components to be simulated in board sim. An example is the HyperLynx DDR3 Wizard, which helps users measure performance of DDR3 memories which can use clock rates in the gigahertz range.

 

XILINX BERR Simulation of Differential Pairs

The Xilinx FPGA tool family includes a simulator which can estimate the BERR of high speed signals connected to the part using models for the connected parts, transmission lines including PCB vias, and a XILINX part model (www.xilinx.com). The BERR simulation tool can plot a color map of an eye diagram showing where transitions occur in simulation over time. XILINX recommends useful sizes of the black open eye region and proximity of signal transitions to the location of a clock edge used to synchronize the differential signals.

 

 

Design Verification in the Lab

 

Design verification of prototypes should be conducted to compare HyperLynx board sim or other tool simulation results with actual prototype signal characteristics across operating condition specs (e.g. temperature).

 

Storage scopes can be used to measure the behavior or high speed signals, eyes of differential pairs, and transmission line characteristics. These tests can be conducted using a pulse generator connected to the source end of the signal to shorten the length of the measurement experiment. Measurements of actual circuit operation are essential, and reveal the effects of noise in the actual environment. Firmware or test hardware for counting errors are useful tools for evaluating transmission lines.

 

 

 

 

Useful Links

 

GTD Design Resource Page

www.gtdigitalsite.org/home/techlinks -

 

Cadence

www.cadence.com

Products

http://www.cadence.com/products/pages/default.aspx

OrCad

http://www.cadence.com/products/orcad/Pages/default.aspx
IP

http://www.chipestimate.com/cadence/

 

Mentor

www.mentor.com

PCB Design Flows

http://www.mentor.com/products/pcb-system-design/design-flows/

PADS PCB Design Solutions

http://www.mentor.com/products/pcb-system-design/design-flows/pads/upload/pads-pcb-design-solutions-27ed8a98-bb2a-4f18-8fa4-cab514ee2826

HyperLynx SI

http://www.mentor.com/products/pcb-system-design/circuit-simulation/hyperlynx-signal-integrity/

 

Xilinx

www.xilinx.com

Xilinx Signal Integrity Link

http://www.xilinx.com/products/technology/signal-integrity/index.htm

Stacked Silicon Interconnect Technology

http://www.xilinx.com/products/technology/stacked-silicon-interconnect/index.htm

Stacked Silicon White Paper

http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf

 

SPICE MODELS

http://homepages.which.net/~paul.hills/Circuits/Spice/SpiceBody.html

SPICE MODELS INDEX

http://homepages.which.net/~paul.hills/Circuits/Spice/ModelIndex.html

 

Analog Devices

A First Approach to IBIS Models: What They Are and How They Are Generated

http://www.analog.com/static/imported-files/application_notes/5935941671412055950152978543245071832296385807601441968349653493056536126553742AN715_0.pdf

 

SISOFT Inc.

Models for SerDes Simulation of Fiber channels. The advanced simulation capabilities of SiSoft’s models include the ability to study the behavior of SERDES parts, which have an extremely large digital design. Fiber interfaces are very reliable (infact, the ATM interface does not have CRC at the individual data frame level, for example, for this reason). When noise simulations are performed, models using the extensive scope of the entire SerDes part design can be useful.

http://www.sisoft.com/elearning/ibis-ami.html

 

Fairchild Application Notes

http://www.fairchildsemi.com/apnotes/apnotesHome

Fairchild IBIS Links

http://www.eda.org/ibis/home/models/

http://www.eda.org/ibis/home/articles/ed_ibis1.htm

 

 

 (copyright)